A simple risc-v single-core CPU design written in Verilog, developed for learning and practicing computer architecture and hardware description languages.
-
Updated
May 28, 2026 - Verilog
#
single-cycle-cpu
Here are 9 public repositories matching this topic...
Single-cycle 32-bit MIPS CPU designed and simulated in Logisim, built for the Computer Architecture Lab (LCOM 3010) at the Islamic University of Gaza. Supports lw, sw, add, sub, and, or, slt, beq, and j.
mips assembly university-project digital-logic computer-architecture logisim digital-design mips-cpu cpu-design single-cycle-cpu
-
Updated
Jul 25, 2026
CO224 Computer Architecture Labs - 8-bit Single-Cycle Processor Implementation .
instruction-set-architecture memory-hierarchy verilog-project cache-implementation single-cycle-cpu alu-design computer-architecture-and-assembly-language 8-bit-processor
-
Updated
Oct 10, 2025 - Verilog
MIPS Processor Implementations (VHDL) | This repository contains multiple implementations of the MIPS (Microprocessor without Interlocked Pipelined Stages) architecture using VHDL. The project is designed for educational and academic purposes, helping students understand CPU architecture and datapath/control design. It includes Single-Cy
mips vhdl computer-organization hardware-design multi-cycle-cpu single-cycle-cpu pipelined-processor-design
-
Updated
Dec 18, 2025 - VHDL
16-bit Single-Cycle CPU designed and verified in Verilog RTL, featuring a custom ISA, 8-bit ALU, register file, instruction memory, branching, jumps, and ModelSim-based verification.
cpu fpga processor rtl verilog hardware-designs computer-architecture modelsim digital-design single-cycle-cpu digital-ic-design
-
Updated
Sep 12, 2026 - Verilog
A single-cycle RISC-V CPU implemented in Verilog, with arithmetic, memory, branch, and jump instructions verified using Icarus Verilog and GTKWave.
processor verilog computer-architecture gtkwave risc-v iverilog digital-design rv32i cpu-design hardware-design single-cycle-cpu
-
Updated
Jun 20, 2026 - Verilog
32-bit Single-Cycle RISC-V (RV32I) CPU built completely from scratch using basic logic primitives and universal NAND gates in Logisim-Evolution. Features full datapath, ALU, Control Unit, 32-register file, Data Memory, and support for R-type, I-type, S-type, and B-type instructions.
assembly riscv isa digital-logic computer-architecture alu logisim rv32i cpu-design hardware-description logisim-evolution single-cycle-cpu nand-to-tetris cpu-from-scratch
-
Updated
Aug 21, 2026
32-bit single-cycle CPU with control unit — Logisim simulation for Computer Organization & Architecture.
mips university-project datapath digital-logic computer-architecture bangladesh logisim computer-organization educational-project control-unit hardware-simulation processor-design cpu-design cse332 register-file north-south-university 32-bit-cpu single-cycle-cpu
-
Updated
Sep 15, 2026
Formally verified, synthesis-ready 8-bit RISC CPU in Verilog. Optimized for efficient hardware implementation.
cpu assembler verilog computer-architecture digital-design logic-design 8-bit-cpu cpu-design custom-cpu single-cycle-cpu digital-design-and-computer-architecture
-
Updated
Aug 10, 2026 - Verilog
Add this topic to your repo
To associate your repository with the single-cycle-cpu topic, visit your repo's landing page and select "manage topics."