riscv32i
Here are 19 public repositories matching this topic...
Risc-V 32i processor written in the Verilog HDL
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Nov 27, 2022 - Verilog
FISC V— Fundamental Instruction Set Computer
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Dec 30, 2025
RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
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Apr 29, 2022 - Python
RISC-V Simulator with RV32IM implementation, built during a few days off.
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Oct 28, 2024 - C
An RP2350 UART driver written entirely in RISC-V Assembler.
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Sep 17, 2026 - Assembly
Neutrino is the logic core of AetherOS. It is a biological Real-Time Operating System (RTOS) developed in RUST and designed to run on bare-metal RISC-V architectures, simulated environments, or biological hardware interfaces.
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Jan 5, 2026 - Rust
A cross-platform RISC-V emulator written in Object Pascal
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Jul 27, 2026 - Pascal
A modular RV32I single-cycle RISC-V processor designed in Systme Verilog for learning and hardware design exploration
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Jul 31, 2026 - SystemVerilog
RISCV 40 Instruction Cycle Accurate CPU Model
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Aug 31, 2026 - Assembly
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