VHDL projects for combinational and sequential logic design on FPGA.
-
Updated
Dec 18, 2024 - VHDL
#
latches
Here are 8 public repositories matching this topic...
Implemented some functionalities for the existing DBMS.
-
Updated
Jul 19, 2021 - C++
🚦 Digital logic implementation of a 4-way intersection traffic light controller using D-flip flops and state machine design. Features timing-based transitions, safe traffic flow management, and complete cycle control for North-South/East-West directions.
-
Updated
May 26, 2025
Gate-level design and simulation of SR, D, JK, and T latches and flip-flops using Intel Quartus.
-
Updated
Sep 13, 2026
Digital Design laboratory project exploring sequential logic circuits, including latches and flip-flops (RS, D, JK, T, Master-Slave), with interactive NI Multisim simulations and detailed documentation (Logic Design, UNIWA).
counter academic-project digital-design sequential-logic multisim logic-circuits flip-flops latches uniwa nand-gates memory-elements
-
Updated
Feb 21, 2026
Verilog code for combinational and sequential circuits
verilog bcd mux hdl multiplexer verilog-hdl moore-machine adders mealy-machine-code flipflop latches synchronous-counter sequentialcircuits shift-registers 7segmentdisplay digitalcircuits flipflop-codes subtractors
-
Updated
Dec 2, 2025 - Verilog
VHDL project for implementing sequential circuits (latches, flip-flops, registers, counters, shift registers) with testbench-based verification in ModelSim (Digital Circuit Design, UNIWA).
simulation vhdl counters academic-project hdl modelsim testbench registers sequential-circuits digital-circuit-design flip-flops latches shift-registers uniwa
-
Updated
Feb 21, 2026 - VHDL
Add this topic to your repo
To associate your repository with the latches topic, visit your repo's landing page and select "manage topics."