eda-automation

MCP server for KiCad, connecting AI agents to schematic and PCB workflows, ERC/DRC validation, DFM checks, BOM analysis, and manufacturing preparation—with controlled edits and human-gated release workflows.

Evidence-first Cadence Allegro footprint automation: datasheet evidence, padstack/package generation, and independent fresh-session verification.

An automated RTL-to-Synthesis EDA tool wrapper written in Tcl. Automates multi-module hierarchy checks, SDC constraint generation, Yosys synthesis mapping, and OpenTimer static timing analysis (STA) for the openMSP430 core.

Engineering traceability framework for Cadence Virtuoso ADE XL using SKILL and Python.

Neural Network models for automating design parameters of CS amplifier. Includes automated SPICE data generation and model validation in Python and MATLAB.

Closed-loop, state-verified Windows automation runtime for AI agents — from EDA and CAD to any desktop application.

AI-native, verification-first EDA kernel for prompt-to-fab electronics: compile design intent into schematics, ERC, placement, routing, DRC, BOM, manufacturing outputs, and auditable proof packs.