Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
explore different implementations of adders and study their characteristics.
Implementation of a Parameterized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
Computer Architecture - Practical Solution with Quartus - Sharif University of Technology
Summary of projects I did in VLSI desing.
Useful VHDL scripts for hardware description.
Different adders code in VHDL and Comparison
Design and FPGA implementation of a Carry Save Adder (CSA) integrated with a Ripple Carry Adder (RCA) using Verilog HDL. Developed and validated in Xilinx Vivado with simulation, synthesis, timing, power, and resource utilization analysis.
Synthesizable high-throughput, energy-optimized Bitcoin Double SHA-256 hardware accelerator in SystemVerilog
32-bit RISC processor designed from scratch in Verilog: Booth bit-pair multiplier with carry-save adder tree, FSM control unit, targeting Intel Cyclone V FPGA.
8×8 unsigned Wallace Tree Multiplier in Verilog using multi-stage 3:2 Carry Save Adders and a Ripple Carry Adder.
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