Summary
The built-in TTL library has no 74HC4015, a dual 4-bit static shift register. This issue tracks adding that digital functional model.
The simulation follows the TI CD74HC4015 and NXP 74HC/HCT4015 data sheets. Each half shifts its serial input into Q0 on the low-to-high clock edge and moves the previous bits toward Q3. A high master reset asynchronously clears that half. The two halves are independent. DIP-16 and SO16 use the same pin numbers.
I expect the 74HC4015 parts to arrive so I can check the model against a physical chip before opening the pull request.
Scope
- Functional model of both 4-bit registers, including the rising-edge shift and asynchronous master reset
- Registration, English and Russian help, and a changelog entry
- VHDL and Verilog model for the two independent clocks
I will open a pull request for this issue after the parts arrive and the breadboard check is done.
Summary
The built-in TTL library has no 74HC4015, a dual 4-bit static shift register. This issue tracks adding that digital functional model.
The simulation follows the TI CD74HC4015 and NXP 74HC/HCT4015 data sheets. Each half shifts its serial input into Q0 on the low-to-high clock edge and moves the previous bits toward Q3. A high master reset asynchronously clears that half. The two halves are independent. DIP-16 and SO16 use the same pin numbers.
I expect the 74HC4015 parts to arrive so I can check the model against a physical chip before opening the pull request.
Scope
I will open a pull request for this issue after the parts arrive and the breadboard check is done.