The built-in TTL library has no 74HC03, a quad 2-input NAND gate with open-drain outputs. This issue tracks adding that digital functional model as 7403.
The simulation follows the Nexperia 74HC03; 74HCT03 data sheet, Rev. 7 (16 February 2024). Each gate drives low only when both inputs are high. Otherwise the output is released (high-impedance). In the simulator a released output is unknown, so an external pull-up can raise it. Pinout is the standard 14-pin package: 1A, 1B, 1Y, 2A, 2B, 2Y, GND, 3Y, 3A, 3B, 4Y, 4A, 4B, VCC. There is no HDL model: open-drain high-impedance is not a push-pull gate network, and the existing open-collector 7438 has none either.
I expect the components to arrive so I can check the model against a physical 74HC03 on a breadboard, driven by an Arduino Nano. I will open a pull request after that check.
The built-in TTL library has no 74HC03, a quad 2-input NAND gate with open-drain outputs. This issue tracks adding that digital functional model as 7403.
The simulation follows the Nexperia 74HC03; 74HCT03 data sheet, Rev. 7 (16 February 2024). Each gate drives low only when both inputs are high. Otherwise the output is released (high-impedance). In the simulator a released output is unknown, so an external pull-up can raise it. Pinout is the standard 14-pin package: 1A, 1B, 1Y, 2A, 2B, 2Y, GND, 3Y, 3A, 3B, 4Y, 4A, 4B, VCC. There is no HDL model: open-drain high-impedance is not a push-pull gate network, and the existing open-collector 7438 has none either.
I expect the components to arrive so I can check the model against a physical 74HC03 on a breadboard, driven by an Arduino Nano. I will open a pull request after that check.