Basys3-Projects

Contains projects implemented on the Basys3 board via Vivado (Verilog)

Name		Name	Last commit message	Last commit date
BRAM-FIFO		BRAM-FIFO
Counter with user-generated freq		Counter with user-generated freq
Division		Division
FSM-sequence		FSM-sequence
GCD of two numbers		GCD of two numbers
Pipelining		Pipelining
SSD and PMOD		SSD and PMOD
door lock		door lock
given function		given function
Basys3_Master.xdc		Basys3_Master.xdc
README.md		README.md
bintoBCD.v		bintoBCD.v
sevenseg_all.v		sevenseg_all.v

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