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gastmaier
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October 1, 2026 14:51
bluncan
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| The Apollo JRx rate match FIFO takes each converter clock worth of samples, | ||
| NS of them, as all valid or all invalid. The FPGA therefore inserts the | ||
| invalid samples in groups of NS samples, NS being the JRx samples per | ||
| converter clock (``ns_minus1 + 1`` of the JRx link). |
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In theory it looks like this FSRC stuff could be a IIO backend cascaded with the axi_adc and axi_dac. But well, apollo is not using it anyways
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would work, requires extending drivers/iio/industrialio-backend.c with at least
iio_backend_rate_ratio_set
iio_backend_sync_start
but migrating apollo to use the backend first you be better, no?
also the sequencer is bizarre; if we had more time the fsrc sequencer core should be replaced with a generic sequencer, it does not do anything but counting til X after Y.
Explain the AD9084's FSRC feature operation and usage. Signed-off-by: Jorge Marques <[email protected]>
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PR Description
Explain the AD9084's FSRC feature operation and usage.
PR Type
PR Checklist