Hi, I'm Atharv Mehrotra

Embedded Systems · VLSI RTL Design · Web Development

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About Me

Undergraduate engineering student working across Embedded Systems, Digital Logic Design, VLSI RTL Design and PCB development.

Primary focus areas:

• VLSI RTL Design
• Embedded Systems

Background experience:

• MERN-based Web Development

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Projects

Domain	Project	Summary
Computer Architecture & RTL	RV32I-SingleCycle-uPCore	A single-cycle RISC-V 32-bit (RV32I) microprocessor core implemented in SystemVerilog.
RTL Design	I2C-SystemVerilog	I2C Master module implementation written in SystemVerilog.
	SPI-Verilog	SPI Master module (Mode 0) written in Verilog.
	UART-Verilog	Universal Asynchronous Receiver/Transmitter implementation in Verilog.
PCB Design	USB-to-UART-CH340G-PCB	2-layer CH340G-based USB-to-UART converter designed using KiCad, featuring a USB-A edge connector and selectable logic levels.
Embedded Systems	ESP-Connect	React Native Android app enabling Bluetooth Classic (SPP) communication with ESP32 for real-time serial exchange.
Web Development	tattva-watch	A full-stack movie discovery platform built with Next.js, featuring user authentication and personalized watchlists.

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Skills & Tools

Software	Hardware
Languages C / C++ Python JavaScript / TypeScript SystemVerilog Verilog SQL Frameworks & Tools React Next.js Node.js MongoDB Git	Embedded & RTL ESP32 Digital Circuit Design PCB & Hardware KiCad (2-Layer PCB Design) VLSI Synthesizable RTL Design in Verilog AMD Vivado Icarus Verilog GTKWave

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Current Technical Direction

• Advancing digital logic design through pipelined architectures and standard communication protocols
• Strengthening computer architecture fundamentals
• Improving PCB layout discipline
• Exploring VLSI physical design concepts

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GitHub Overview

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Connect

       

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