RISC-V (RV32I) Single-Cycle CPU Built From NAND Gates

A 32-bit single-cycle RISC-V processor built from basic logic primitives (NAND gates) up to a fully functional CPU capable of executing ISA instructions.

📌 Architecture Overview

• ISA: RISC-V (RV32I Base Integer Instruction Set)
• Design Type: Single-Cycle Datapath
• Base Primitive: Universal NAND logic gates
• Environment: Logisim-evolution

🏗 Submodule Hierarchy

1. Primitives: Universal NAND-logic gates, Multiplexers, Decoders.
2. Sequential Logic: D-Flip-Flops, Registers, 32-bit Register File.
3. ALU & Arithmetic: 32-bit Adder, Arithmetic Logic Unit with zero-detection.
4. Datapath & Control: Main Control Unit, Extend unit, PC logic, Memory interfaces.

🧪 Verified Instructions

• addi — Immediate Addition
• add — Register Addition
• sw — Store Word to Data Memory
• lw — Load Word from Data Memory
• beq — Branch if Equal (Conditional Jump)

📋 Supported Instructions

• Arithmetic (R-Type): add, sub, xor, or, and, slt
• Arithmetic Immediate (I-Type): addi, xori, ori, andi, slti
• Memory Access: lw (Load Word), sw (Store Word)
• Control Flow: beq (Branch if Equal)

🚀 Quick Start

1. Install Logisim-evolution.
2. Open src/cpu/SingleCycleProcessor.circ.
3. Load hex binaries from tests/ into Instruction Memory (ROM).
4. Enable Clock Ctrl + K or step through manually.